This invention relates to an art of FM modulation through digital signal processing for FM modulation by using a quadrature-phase modulator.
A conventional portable phone such as a cellular phone has generally used an FM modulation system. Recently a digital cellular system employing digital modulation has used a quadrature-phase modulator as a modulation circuit, especially used for the digital system.
In a specific area such as North America, however, the use of dual mode system as a combination of digital modulation and conventional analogue FM modulation in a portable phone has been specified as a next-generation cellular unit in view of compatibility with the conventional analogue cellular unit.
In order to realize the specified dual mode system, it is necessary to mount both quadrature-phase modulator and the analogue FM modulator in a unit.
Most of conventional FM modulations for the analogue cellular unit have been designed to modulate an oscillator directly with a voltage controlled oscillator (VCO). While a digital cellular unit uses modulation systems such as .rho./4 shift DQPSK, GMSK, QPSK, offset QPSK, and the like processed through a quadrature-phase modulator.
The North American area has specified the use of the dual mode system as a combination of the digital modulation system and conventional analogue cellular. So a compact portable phone has to be provided with both FM modulation and quadrature-phase modulation functions therein.
Realizing those functions in the respective circuits requires a number of parts, thus failing to realize the compact unit at a low price. As a result, the FM modulation eventually demands the use of a quadrature-phase modulator as its indispensable component.
With the above method, an input signal for FM modulation is A/D converted to produce an in-phase input signal I and a quadrature-phase input signal Q as base band input signals for the quadrature-phase modulation through digital signal processing, which are supplied to the quadrature-phase modulator.
A publication of Japanese Patent Laid-Open No. 3-60502(1991) titled "Digital FM modulator" has disclosed a method for generating the aforementioned in-phase input signal I and the quadrature-phase input signal Q from the input modulation signal. The disclosed method is hereinafter explained referring to the drawing.
FIG. 5 shows a digital FM modulator based on the disclosed method. The digital FM modulator comprises an integrator 70 for integrating an input modulation signal supplied to an input terminal 71, and a phase modulator 40 for phase modulating an output of the integrator 70.
The integrator 70 comprises a delay register 73 for executing 1 sampling cycle delay, and an adder 74 for adding the output of the register 73 to the input modulation signal, which functions in integrating by adding the input modulation signal to the output of the register 73 sequentially by each sample.
The output of the integrator 70 is derived from integrating the output of the modulation signal proportional to frequency to become a phase signal. The phase signal is input to the phase modulator 40. Using the input phase signal as an address, values stored in cosine ROM 42 and sine ROM 43 are read as the in-phase input signal I and the quadrature-phase input signal Q, respectively.
FIG. 6 shows stored contents of the cosine ROM 42 and sine ROM 43. In FIG. 6, an axis of ordinate denotes the stored contents of the ROMs, and an axis of abscissa denotes the address.
The in-phase input signal I and the quadrature-phase input signal Q output from the cosine ROM 42 and sine ROM 43 are multiplied with carrier signals with phase shifted by 90.degree. at multipliers 45 and 46, respectively, which are added together at an adder 49. The addition result is converted into an analogue signal through a D/A converter 50. After eliminating unnecessary wave of the converted analogue signal at a band pass filter 51, it is output as an FM modulated signal 52.
This example intends to apply video signals of a video recorder to FM modulation with a carrier at a low frequency. Its quadrature-phase modulator is realized through digital signal processing.
In another prior art relevant to this invention, "Digitized quadrature-phase modulator" has been disclosed in a publication of Japanese Patent Laid-Open No. 3-179954 (1991) (hereinafter referred to as Prior Art 1). The disclosed modulator is so constructed to operate a counter ROM with a phase shifted by 180.degree. and an operation for the part unselected from a data selector has been preliminary omitted to decrease the speed to access the ROM with operation results by half compared with conventional access speed.
In the Prior Art 1, an in-phase input signal and quadrature-phase input signal are respectively stored in a first and a second shift registers sequentially where clock signals at a predetermined frequency are supplied from a clock control circuit, which assigns low significant addresses to a first ROM and a second ROM, respectively. The first ROM and the second ROM receive the low significant addresses from the first counter and the second counter. The first ROM and the second ROM, then, output the first and the second 1 bit signals. The first and the second 1 bit signals are alternately selected by a data selector to be output as a selected 1 bit signal. The selected 1 bit signal is formed into a digital analogue signal with its analogue signal output as a modulation output signal.
A publication of Japanese Patent Laid-Open No. 2-266705 (1990) (hereinafter referred to as Prior Art 2) has disclosed "FM modulator" for multiplying quadrature first and second modulation signals and quadrature first and second carrier signals to be added to provide an output having excellent linearity with no high-order bias.
The Prior Art 2 converts an input digital video signal into two quadrature digital video signals. A phase modulator receives quadrature first and second carrier signals. The first modulation signal and the first carrier signal are supplied to a first multiplier, and the second modulation signal and the second carrier signal are supplied to a second multiplier, respectively. The multiplied outputs of the first and the second multipliers are added through the adder to provide an output in which the only phase of the second carrier signal is modulated. This may eliminate non-linearity in the input of voltage-to-output frequency as well as high-order bias contained in the FM modulated wave.
A publication of Japanese Patent Laid-Open No. 2-220537 (1990) (hereinafter referred to as Prior Art 3) has disclosed "Quadrature-phase modulator" which allows modulation signals to be output without changing the condition of waveform shaping through a MOSFET analogue filter with variable frequency characteristics to provide a monolithic integrated quadrature-phase modulator with high accuracy.
In the Prior Art 3, an input signal is input to a digital signal processing circuit through a switch. The digital signal processing circuit outputs 2 lines of digital signals with each phase orthogonalized with each other. The 2 lines of digital signals are D/A converted through a first and a second D/A converters to be input to a first and a second multipliers via a first and a second MOSFET analogue filters, respectively. The first and the second multipliers multiply outputs of the first and the second MOSFET analogue filters with carrier waves with each phase orthogonal thereto. The multiplication results of the first and the second multipliers are further added through the adder to be output. In this case, clock signals of the signal input to the digital signal processing circuit allow the frequency characteristics of the first and the second MOSFET analogue filters to be varied so as to eliminate harmonics component contained in the output signals of the first and the second D/A converters.
The aforementioned Prior Arts obtain an in-phase input signal I and a quadrature-phase input signal Q by integrating the input modulation signal, and reading the cosine ROM and the sine ROM using integrated results as addresses. A large capacity of cosine ROM and sine ROM are eventually required by enlarging the chip size in the form of LSI, resulting in price increase.
The Prior Art 1 requires the ROMs, thus having the same drawback as aforementioned. The Prior Art 2 also requires a large capacity of cosine ROMs and sine ROMs. The Prior Art 3 has a digital signal processing circuit for outputting 2 lines of digital signals with each phase orthogonalized thereto, however, detailed construction of the circuit has not been described.